Simulation Timer_2

Control:						Mem:					Aide

Source

001 8080 ; This is a complete simulation of a micro-controler on line
002 8080 ; designed for beginers
003 8080 ; and very useful during Covid19 lockdown
004 8080 ;
005 8080 ; - Major opcodes and devices are operationnal
006 8080 ; - You can debug step by step, use breakpoint
007 8080 ; - The assembly language is fully compliant with the standard
008 8080 ; - Everything(~) works except the real time
009 8080 ;
010 8080 ; If you are interested, please send us an email at info@veymont-tech.com
011 8080 ;
012 8080 ; NOTE Demos are limited to 256 instructions cycles (cf. grey counter)
013 8080 ;
014 8080 ; Source program is a standard Stm8 assembly file
015 8080 ; Displayed devices are defined in a SVG file
016 8080 synoptic EQU "CRiZP@Kr"
017 8080 
018 8080 ; TIMER_2
019 8080 ; Addresses are those for STM8S105
020 8080 TIM2_CR1   EQU $5300 ; control register 1
021 8080 TIM2_IER   EQU $5303 ; interrupt enable regsiter
022 8080 TIM2_SR1   EQU $5304 ; status register
023 8080 TIM2_EGR   EQU $5306 ; event generation register
024 8080 TIM2_CNTRH EQU $530C ; counter register
025 8080 TIM2_CNTRL EQU $530D
026 8080 TIM2_PSCR  EQU $530E ; prescaler register
027 8080 TIM2_ARRH  EQU $530F ; auto-reload register
028 8080 TIM2_ARRL  EQU $5310 ;
029 8080 
030 8080 ; Related masks
031 8080 TIM2_CR1_ARPE EQU $80 ; auto-reload preload enable mask
032 8080 TIM2_CR1_OPM  EQU $08 ; one pulse mode mask
033 8080 TIM2_CR1_URS  EQU $04 ; update request source mask
034 8080 TIM2_CR1_UDIS EQU $02 ; update disable mask
035 8080 TIM2_CR1_CEN  EQU $01 ; counter enable
036 8080 TIM2_IER_UIE  EQU $01 ; update interrupt enable mask
037 8080 TIM2_SR1_UIF  EQU $01 ; update interrupt flag mask
038 8080 TIM2_EGR_UG   EQU $01 ; update generation mask
039 8080 TIM2_PSCR_PSC EQU $07 ; prescaler value mask
040 8080 
041 8080 ; GPIOs
042 8080 PA_ODR EQU $5000
043 8080 PA_IDR EQU $5001
044 8080 PA_DDR EQU $5002
045 8080 PA_CR1 EQU $5003
046 8080 PA_CR2 EQU $5004
047 8080 
048 8080 PB_ODR EQU $5005
049 8080 PB_IDR EQU $5006
050 8080 PB_DDR EQU $5007
051 8080 PB_CR1 EQU $5008
052 8080 PB_CR2 EQU $5009
053 8080 
054 8080 PC_ODR EQU $500A
055 8080 PC_IDR EQU $500B
056 8080 PC_DDR EQU $500C
057 8080 PC_CR1 EQU $500D
058 8080 PC_CR2 EQU $500E
059 8080 
060 8080 ; Number masks
061 8080 ZERO       EQU $FC
062 8080 ONE        EQU $60
063 8080 TWO        EQU $DA
064 8080 
065 8080 
066 8080 Data segment byte at: 00-10 'Ram'
067 0000 ; Page 0 variables
068 0000 cnt ds.b  ; my loop counter
069 0001 addresse ds.w ; any addresse
070 0003 
071 0003 Stack_seg segment byte at: 7F0-7FF 'Ram'
072 07F0 
073 07F0 Gpio_seg segment byte at: 5000-5010 'Gpio'
074 5000 
075 5000 Tim2_seg segment byte at: 5300-5310 'Tim2'
076 5300 
077 5300 ; Interrupt vectors
078 5300 vectit segment byte at: 8000-807F 'Flash'
079 8000     INT Start                ; reset
080 8004     INT NonHandledInterrupt  ; trap
081 8008     INT NonHandledInterrupt  ; irq0 TLI External top level interrupt
082 800C     INT NonHandledInterrupt  ; irq1 AWU Auto wake up from halt
083 8010     INT NonHandledInterrupt  ; irq2 CLK Clock Controller
084 8014     INT NonHandledInterrupt  ; irq3 EXTIO Port A external
085 8018     INT NonHandledInterrupt  ; irq4 EXTI1 Port B
086 801C     INT NonHandledInterrupt  ; irq5 EXTI2 Port C
087 8020     INT NonHandledInterrupt  ; irq6 EXTI3 Port D
088 8024     INT NonHandledInterrupt  ; irq7 EXTI4 Port E external
089 8028     INT NonHandledInterrupt  ; irq8  reserved
090 802C     INT NonHandledInterrupt  ; irq9  reserved
091 8030     INT NonHandledInterrupt  ; irq10 SPI end of transfer
092 8034     INT NonHandledInterrupt  ; irq11 TIM1 Update/overflow/underflow/trigger/break
093 8038     INT NonHandledInterrupt  ; irq12 TIM1 Capture/Compare
094 803C     INT TIM2_Update          ; irq13 TIM2 update/overflow
095 8040     INT NonHandledInterrupt  ; irq14 TIM2 capture / compare
096 8044     INT NonHandledInterrupt  ; irq15 TIM3 Update/ overflow
097 8048     INT NonHandledInterrupt  ; irq16 TIM3 Capture / Compare
098 804C     INT NonHandledInterrupt  ; irq17 reserved
099 8050     INT NonHandledInterrupt  ; irq18 reserved
100 8054     INT NonHandledInterrupt  ; irq19 I2C
101 8058     INT NonHandledInterrupt  ; irq20 Uart2 Tx Complete
102 805C     INT NonHandledInterrupt  ; irq21 Uart2 Receive Register Data Full
103 8060     INT NonHandledInterrupt  ; irq22 ADC1 end of conversion
104 8064     INT NonHandledInterrupt  ; irq23 TIM4 Update/Overflow
105 8068     INT NonHandledInterrupt  ; irq24 Flash EOP/WR_PG_DIS
106 806C     INT NonHandledInterrupt  ; irq25 reserved
107 8070     INT NonHandledInterrupt  ; irq26 reserved
108 8074     INT NonHandledInterrupt  ; irq27 reserved
109 8078     INT NonHandledInterrupt  ; irq28 reserved
110 807C     INT NonHandledInterrupt  ; irq29 reserved
111 8080 
112 8080 
113 8080 ; Code segment in flash
114 8080 code segment byte at: 8080-80C0 'Flash'
115 8080 Start
116 8080    ; Led configuration
117 8080    LDW X,#PB_ODR  ; parameters X = PB_ODR
118 8083    LD A,#$FF      ;            A = All 8 pins
119 8085    CALL gpio_output_init
120 8088    LD A,#ZERO
121 808A    LD PB_ODR,A
122 808D 
123 808D    ; Timer2 initialization
124 808D    ; With a real micro-controler tim2 would be initialized so
125 808D    ;MOV TIM2_PSCR,#14  ; 16384, 16 MHz/16384 == 976,5625 Hz
126 808D    ;MOV TIM2_ARRH,#$03 ; ARR == 0x03DA environ 1Hz
127 808D    ;MOV TIM2_ARRL,#$D1
128 808D    ; But with the simulator we have adaptated so
129 808D    MOV TIM2_PSCR,#1  ; 16384, 16 MHz/16384 == 976,5625 Hz
130 8091    MOV TIM2_ARRH,#$00 ; ARR == 0x03DA environ 1Hz
131 8095    MOV TIM2_ARRL,#$10
132 8099 
133 8099    ; Update interrupt enabled
134 8099    LD A,TIM2_IER
135 809C    OR A,#TIM2_IER_UIE
136 809E    LD TIM2_IER,A
137 80A1  
138 80A1    ; Timer enabled
139 80A1    LD A,TIM2_CR1
140 80A4    OR A,#TIM2_CR1_CEN
141 80A6    LD TIM2_CR1,A
142 80A9    
143 80A9    CLR cnt
144 80AB 
145 80AB my_loop 
146 80AB    JRA my_loop
147 80AD 
148 80AD    ; GPIO input initialization, parameters X -> Port, A -> Lines Mask
149 80AD    ; Px_DDR = Px_DDR & ^ Masque
150 80AD gpio_input_init PUSH A
151 80AE    CPL A 
152 80AF    AND A,($2,X)
153 80B1    LD ($2,X),A
154 80B3    ; Px_CR1 = Px_CR1 & ^ Mask
155 80B3    LD A,($1,SP) 
156 80B5    CPL A 
157 80B6    AND A,($3,X)
158 80B8    LD ($3,X),A
159 80BA    ; Px_CR2 = Px_CR2 & ^ Mask
160 80BA    LD A,($1,SP) 
161 80BC    CPL A 
162 80BD    AND A,($4,X)
163 80BF    LD ($4,X),A
164 80C1    POP A
165 80C2    RET
166 80C3 
167 80C3    ; GPIO output initialization, parameters: X -> Port, A -> Mask
168 80C3    ; Px_DDR = Px_DDR | Mask
169 80C3 gpio_output_init PUSH A
170 80C4    OR A,($2,X)
171 80C6    LD ($2,X),A
172 80C8    ; Px_CR1 = Px_CR1 & ^ Mask
173 80C8    LD A,($1,SP) 
174 80CA    CPL A 
175 80CB    AND A,($3,X)
176 80CD    LD ($3,X),A
177 80CF    ; Px_CR2 = Px_CR2 & ^ Mask
178 80CF    LD A,($1,SP) 
179 80D1    CPL A 
180 80D2    AND A,($4,X)
181 80D4    LD ($4,X),A
182 80D6    POP A
183 80D7    RET
184 80D8 
185 80D8    INTERRUPT NonHandledInterrupt
186 80D8 NonHandledInterrupt
187 80D8     iret
188 80D9 
189 80D9    ; My real interrupt routine!
190 80D9    INTERRUPT TIM2_Update
191 80D9 TIM2_Update ; Simple blink
192 80D9    LD A,PB_ODR
193 80DC    AND A,#$80
194 80DE    JREQ not_equal
195 80E0    LD A,#ONE
196 80E2    JRA end_tim2_update
197 80E4 not_equal LD A,#TWO
198 80E6 end_tim2_update LD PB_ODR,A
199 80E9    IRET
200 80EA 
201 80EA